1 pi6c49x0204a block diagram description the pi6c49x0204a is a low skew, single input to four output, clock buffer. perfect for fanning out multiple clock outputs. low skew 1 to 4 clock buffer features ? ? low skew outputs (250 ps) ? ? packaged in 8-pin soic ? ? low power cmos technology ? ? operating voltages of 1.5 v to 3.3 v ? ? output enable pin tri-states outputs ? ? 3.6 v tolerant input clock ? ? industrial temperature ranges q0 output enable clk q1 q2 q3 pin assignment 1 5 6 7 8 4 3 2 v dd gnd q3 clk oe q2 q1 q4 pi6c49x0204a rev c 5/1 1/2015 15-0061
2 pin# pin name pin ty pe pin description 1 clk input clock input. 3.3 v tolerant input. 2 q1 output clock output 1. 3 q2 output clock output 2. 4 q3 output clock output 3. 5 q4 output clock output 4. 6 gnd power connect to ground. 7 vdd power connect to 1.5 v, 1.8v, 2.5v or 3.3v. 8 oe input output enable. tri-states outputs when low. connect to vdd for normal operation. pin descriptions external components a minimum number of external components are required for proper operation. a decoupling capacitor of 0.01 f should be connected between vdd on pin 7 and gnd on pin 6, as close to the device as possible. a 33 series terminating resistor may be used on each clock output if the trace is longer than 1 inch. pi6c49x0204a rev c 5/1 1/2015 pi6c49x0204a low skew 1 to 4 clock buffer 15-0061
3 maximum ratings supply voltage, vdd ................................... 4.6 v output enable and all outputs ............ -0.5 v to vdd+0.5 v clk ........................... -0.5 v to 3.6 v (vdd > 0v) ambient operating temperature (industrial) ....... -40 to +85 c storage temperature ......................... -65 to +150c junction temperature ................................ 125c soldering temperature ............................... 260c esd protection (hbm) ................................ 2000 v note: stresses above the ratings listed below can cause permanent damage to the pi6c49x0204a. functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifcations is not implied. exposure to absolute maximum rating conditions for extended periods can affect product reliability. electrical parameters are guaranteed only over the recommended operating temperature range. recommended operation conditions parameter min. ty p. max. units ambient operating temperature (industrial) -40 +85 c power supply voltage (measured in respect to gnd) +1.425 +3.6 v pi6c49x0204a rev c 5/1 1/2015 pi6c49x0204a low skew 1 to 4 clock buffer 15-0061
4 vdd=1.5 v 5%, ambient temperature -40 to +85 c, unless stated otherwise ymbol arameter conditions in. y p. a. nits vdd operating voltage 1.425 1.5 1.575 v v ih input high voltage note 1, clk 1.17 3.6 v v il input low voltage note 1, clk 0.575 v i ih input high current note 1, clk, oe 40 a i il input low current note 1, clk, oe 1 a v oh output high voltage i oh = -6 ma 0.95 v v ol output low voltage i ol = 6 ma 0.45 v idd operating supply current no load, 133 mhz 20 ma z o nominal output impedance 20 c in input capacitance clk, oe pin 5 pf i os short circuit current 12 ma notes: 1. nominal switching threshold is vdd/2 dc electrical characteristics vdd=1.8 v 5%, ambient temperature -40 to +85 c, unless stated otherwise ymbol arameter conditions in. y p. a. nits vdd operating voltage 1.7 1.8 1.89 v v ih input high voltage note 1, clk 1.7 3.6 v v il input low voltage note 1, clk 0.6 v i ih input high current note 1, clk, oe 50 a i il input low current note 1, clk, oe 1 a v oh output high voltage i oh = -8 ma 1.4 v v ol output low voltage i ol = 8 ma 0.4 v idd operating supply current no load, 133 mhz 20 ma z o nominal output impedance 20 c in input capacitance clk, oe pin 5 pf i os short circuit current 20 ma notes: 1. nominal switching threshold is vdd/2 pi6c49x0204a rev c 5/1 1/2015 pi6c49x0204a low skew 1 to 4 clock buffer 15-0061
5 vdd=2.5 v 5%, ambient temperature -40 to +85 c, unless stated otherwise ymbol arameter conditions in. y p. a. nits vdd operating voltage 2.375 2.5 2.625 v v ih input high voltage note 1, clk 1.7 3.6 v v il input low voltage note 1, clk 0.7 v i ih input high current note 1, clk, oe 60 a i il input low current note 1, clk, oe 3 a v oh output high voltage i oh = -8 ma 2 v v ol output low voltage i ol = 8 ma 0.4 v idd operating supply current no load, 133 mhz 25 ma z o nominal output impedance 20 c in input capacitance clk, oe pin 5 pf i os short circuit current 50 ma notes: 1. nominal switching threshold is vdd/2 vdd=1.5 v 5%, ambient temperature -40 to +85 c, unless stated otherwise ymbol arameter conditions in. y p. a. nits f out output frequency 0 166 mhz tor output rise time 20% to 80% 1.0 1.5 ns tof output fall time 20% to 80% 1.0 1.5 ns t pd propagation delay (note1) 2 3 5 ns t sk output to output skew (note2) rising edges at vdd/2 0 250 ps ac electrical characteristics vdd=3.3 v 10%, ambient temperature -40 to +85 c, unless stated otherwise ymbol arameter conditions in. y p. a. nits vdd operating voltage 3.0 3.3 3.6 v v ih input high voltage note 1, clk 2.1 3.6 v v il input low voltage note 1, clk 0.7 v i ih input high current note 1, clk, oe 85 a i il input low current note 1, clk, oe 1 a v oh output high voltage i oh = -8 ma 2.8 v v ol output low voltage i ol = 8 ma 0.2 v idd operating supply current no load, 133 mhz 33 ma z o nominal output impedance 20 c in input capacitance clk, oe pin 5 pf i os short circuit current 50 ma notes: 1. nominal switching threshold is vdd/2 pi6c49x0204a rev c 5/1 1/2015 pi6c49x0204a low skew 1 to 4 clock buffer 15-0061
6 vdd=1.8 v 5%, ambient temperature -40 to +85 c, unless stated otherwise ymbol arameter conditions in. y p. a. nits f out output frequency 0 166 mhz tor output rise time 20% to 80% 1.0 1.5 ns tof output fall time 20% to 80% 1.0 1.5 ns t pd propagation delay (note1) 1.6 2 3 ns t sk output to output skew (note2) rising edges at vdd/2 0 250 ps j add additive jitter @156.25mhz, 12k to 20mhz 0.1 ps ac electrical characteristics vdd=2.5 v 5%, ambient temperature -40 to +85 c, unless stated otherwise ymbol arameter conditions in. y p. a. nits f out output frequency 0 200 mhz tor output rise time 20% to 80% 1.0 1.5 ns tof output fall time 20% to 80% 1.0 1.5 ns t pd propagation delay (note1) 0.8 1.0 1.5 ns t sk output to output skew (note2) rising edges at vdd/2 0 250 ps j add additive jitter @156.25mhz, 12k to 20mhz 0.05 ps notes: 1. with rail to rail input clock 2. between any 2 outputs with equal loading. thermal characteristics smol parameter conditions min. t p. max. units ja thermal resistance junction to ambient still air 157 c/w jc thermal resistance junction to case 42 c/w vdd=3.3 v 10%, ambient temperature -40 to +85 c, unless stated otherwise ymbol arameter conditions in. y p. a. nits f out output frequency 0 200 mhz tor output rise time 20% to 80% 1.0 1.5 ns tof output fall time 20% to 80% 1.0 1.5 ns t pd propagation delay (note1) 0.8 1.0 1.5 ns t sk output to output skew (note2) rising edges at vdd/2 0 250 ps j add additive jitter @156.25mhz, 12k to 20mhz 0.05 ps notes: 1. with rail to rail input clock 2. between any 2 outputs with equal loading. pi6c49x0204a rev c 5/1 1/2015 pi6c49x0204a low skew 1 to 4 clock buffer 15-0061
7 phase noise plot pi6c49x0204a rev c 5/1 1/2015 pi6c49x0204a low skew 1 to 4 clock buffer 15-0061
8 suggest for unused inputs and outputs lvcmos input control pins it is suggested to add pull-up=4.7k and pull-down=1k for lvc - mos pins even though they have internal pull-up/down but with much higher value (>=50k) for higher design reliability. outputs all unused outputs are suggested to be lef open and not con - nected to any trace. fis can lower the ic power consumption. power decoupling & routing vdd pin decoupling each vdd pin must have a 0.1uf decoupling capacitor. for better decoupling, 1uf can be used. locating the decoupling capacitor on the component side has better decoupling flter result as shown. cmos clock trace routing please ensure that there is a sufcent keep-out area to the adja - cent trace (>20mil.). in an example using a 125mhz xo driving a bufer ic, it is better to route the clock trace on the component side with a 33 ohm termination resistor. placement of decoupling caps clock ic device vdd 11 13 10 9 8 12 14 0.1uf 0.1uf gnd gnd vdd vdd decouple cap. on comp. side gnd application information cmos output termination popular cmos output termination fe most popular cmos termination is a serial resitor close to the output pin (<=200mil). it is simple and balances the drive strength. fe resistor's value can be fne tuned for best perfor - mance during board bring-up based on vddo voltage used. combining serial and parallel termination designers can also use a parallel termination for cmos outputs. for example, a 50 ohm pull-down resistor can be used at the rx side to reduce signal refection, but it reduces the signals v_swing in half. fis pull-down can be combined with a serial resitor to form a smaller clock voltage diference. fe following diagram shows how to transition a 2.5v clock into 1.8v clock. rs = 33 ohm with rn = 100 ohm, to transition 3.3v cmos to 2.5v rs= 43 ohm with rn =70 ohm to transition 3.3v cmos to 1.8v pi6c49x0204a rev c 5/1 1/2015 pi6c49x0204a low skew 1 to 4 clock buffer 15-0061
9 clock jitter defnitions total jitter= rj + dj random jitter (rj) is unpredictable and unbounded timing noise that can ft in a gaussian math distribution in rms. rj test val - ues are directly related with how long or how many test samples are available. deterministic jitter (dj) is timing jitter that is pre - dictable and periodic in fxed interference frequency. total jitter (tj) is the combination of random jitter and deterministic jitter: , where is a factor based on total test sample count. jedec std. specifes digital clock tj in 10k random samples. phase jitter phase noise is short-term random noise attached on the clock carrier and it is a function of the clock ofset from the car - rier, for example dbc/hz@10khz which is phase noise power in 1-hz normalized bandwidth vs. the carrier power @10khz ofset. integration of phase noise in plot over a given frequency band yields rms phase jitter, for example, to specify phase jitter <=1ps at 12k to 20mhz ofset band as sonet standard specif - cation. device thermal calculation fe jedec thermal model in a 4-layer pcb is shown below. jedec ic fermal model important factors to infuence device operating temperature are: 1) fe power dissipation from the chip (p_chip) is afer subtract - ing power dissipation from external loads. generally it can be the no-load device idd 2) package type and pcb stack-up structure, for example, 1oz 4 layer board. pcb with more layers and are thicker has better heat dissipation 3) chassis air fow and cooling mechanism. more air fow m/s and adding heat sink on device can reduce device fnal die junc - tion temperature tj fe individual device thermal calculation formula: tj =ta + pchip x ja tc = tj - pchip x jc ja ___ package thermal resistance from die to the ambient air in c/w unit; fis data is provided in jedec model simulation. an air fow of 1m/s will reduce ja (still air) by 20~30% jc ___ package thermal resistance from die to the package case in c/w unit tj ___ die junction temperature in c (industry limit <125c max.) ta ___ ambiant air temprature in c tc ___ package case temperature in c pchip___ ic actually consumes power through iee/gnd cur - rent pi6c49x0204a rev c 5/1 1/2015 pi6c49x0204a low skew 1 to 4 clock buffer 15-0061
10 ordering information (1-3) ordering code package code package description pi6c49x0204awie w 8-pin, pb-free & green, soic PI6C49X0204AWIEX w 8-pin, pb-free & green, soic, tape & reel notes: 1. thermal characteristics can be found on the company web site at www .pericom.com/packaging/ 2. e = pb-free and green 3. adding an x suffx = tape/reel pericom semiconductor corporation ? 1-800-435-2336 ? www .pericom.com note: ? for latest package info, please check: http://www.pericom.com/products/packaging/mechanicals.php all trademarks are property of their respective owners. pi6c49x0204a rev c 5/1 1/2015 pi6c49x0204a low skew 1 to 4 clock buffer 15-0061
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